The present invention relates in general to a semiconductor device having a CSP (Chip Size Package) configuration, or the like, wherein a semiconductor chip is mounted over a wiring board, and, more particularly, the invention relates to a technique for improving noise caused by a wiring routing arrangement provided over a wiring board, e.g., a technique that is effective when applied to a synchronous SRAM (Static Random Access Memory), or the like, that is memory-operated in a DDR (Double Data Rate) mode.
A clock synchronized memory, such as a synchronous SRAM, outputs a clock signal that is synchronized with a data output timing in order to indicate timing provided to determine read data to an access main body. Such a clock signal is called an “echo clock” with respect to an input clock signal that is used for a clock synchronous operation. In the synchronous SRAM, it is always outputted and operated regardless of read and write operations as a free running echo clock. The echo clock has been described in a patent document 1 (Japanese Unexamined Patent Publication No. 2003-36700).
A BGA or the like has been adopted for an LSI package to obtain a multi-pin configuration of an LSI and a reduction in chip size. A patent document 2 (Japanese Unexamined Patent Publication No. Hei 11(1999)-97613) has disclosed an LSI package technique wherein, in order to prevent the occurrence of noise due to crosstalk at the LSI package using BGA or the like, a signal group is divided into a signal group susceptible to noise, a signal group apt to emit noise, etc., and terminals are assigned to provide mutual separation.
A patent document 3 (Japanese Unexamined Patent Publication No. Hei 7(1995)-283340) has described a technique wherein, in a PGA (Pin Grid Array) package, ground pins surround a plurality of signal lines to perform isolation among signals.